Bücher von Catherine C. McGeoch

Adiabatic quantum computation (AQC) is an alternative to the better-known gate model of quantum computation. The two models are polynomially equivalent, but otherwise quite dissimilar: one property that distinguishes AQC from the gate model is its analog nature. Quantum annealing (QA) describes a type of heuristic search algorithm that can be implemented to run in the ``native instruction set'' of an AQC platform. D-Wave Systems Inc. manufactures {quantum annealing processor chips} that exploit quantum properties to realize QA computations in hardware. The chips form the centerpiece of a novel computing platform designed to solve NP-hard optimization problems. Starting with a 16-qubit prototype announced in 2007, the company has launched and sold increasingly larger models: the 128-qubit D-Wave One system was announced in 2010 and the 512-qubit D-Wave Two system arrived on the scene in 2013. A 1,000-qubit model is expected to be available in 2014. This monograph presents an introductory overview of this unusual and rapidly developing approach to computation. We start with a survey of basic principles of quantum computation and what is known about the AQC model and the QA algorithm paradigm. Next we review the D-Wave technology stack and discuss some challenges to building and using quantum computing systems at a commercial scale. The last chapter reviews some experimental efforts to understand the properties and capabilities of these unusual platforms. The discussion throughout is aimed at an audience of computer scientists with little background in quantum computation or in physics. Table of Contents: Acknowledgments / Introduction / Adiabatic Quantum Computation / Quantum Annealing / The D-Wave Platform / Computational Experience / Bibliography / Author's Biography

The Workshop on Experimental Algorithms, WEA, is intended to be an int- national forum for research on the experimental evaluation and engineering of algorithms, as well as in various aspects of computational optimization and its applications. The emphasis of the workshop is the use of experimental me- ods to guide the design, analysis, implementation, and evaluation of algorithms, heuristics, and optimization programs. WEA 2008 was held at the Provincetown Inn, Provincetown, MA, USA, on May 30 - June 1, 2008. This was the seventh workshop of the series, after Rome (2007),Menorca(2006),Santorini(2005),RiodeJaniero(2004),Asconia(2003), and Riga (2001). This volume contains all contributed papers accepted for presentation at the workshop. The 26 contributed papers were selected by the Program Committee onthebasisofatleastthreerefereereports,somecontributedbytrustedexternal referees. In addition to the 26 contributed papers, the program contained two invited talks. Camil Demetrescu, of the University of Rome "e;La Sapienza,"e; spoke on "e;Visualization in Algorithm Engineering."e; David S. Johnson of AT & T Labs - Research, gave a talk on "e;Bin Packing: From Theory to Experiment and Back Again."e; We would like to thank the authors who responded to the call for papers, our invited speakers, the members of the ProgramCommittee, the external referees, and the Organizing Committee members for making this workshop possible.

Symmetric multiprocessors (SMPs) dominate the high-end server market and are currently the primary candidate for constructing large scale multiprocessor systems. Yet, the design of e cient parallel algorithms for this platform c- rently poses several challenges. The reason for this is that the rapid progress in microprocessor speed has left main memory access as the primary limitation to SMP performance. Since memory is the bottleneck, simply increasing the n- ber of processors will not necessarily yield better performance. Indeed, memory bus limitations typically limit the size of SMPs to 16 processors. This has at least twoimplicationsfor the algorithmdesigner. First, since there are relatively few processors availableon an SMP, any parallel algorithm must be competitive with its sequential counterpart with as little as one processor in order to be r- evant. Second, for the parallel algorithm to scale with the number of processors, it must be designed with careful attention to minimizing the number and type of main memory accesses. In this paper, we present a computational model for designing e cient al- rithms for symmetric multiprocessors. We then use this model to create e cient solutions to two widely di erent types of problems - linked list pre x com- tations and generalized sorting. Both problems are memory intensive, but in die rent ways. Whereas generalized sorting algorithms typically require a large numberofmemoryaccesses, they areusuallytocontiguousmemorylocations. By contrast, prex computation algorithms typically require a more modest qu- tity of memory accesses, but they are are usually to non-contiguous memory locations.