Bücher von Georges Gielen

This book demonstrates why highly-digital CMOS time-encoding analog-to-digital converters incorporating voltage-controlled oscillators (VCOs) and time-to-digital converters (TDCs) are a good alternative to traditional switched-capacitor S-D modulators for power-efficient sensor, biomedical and communications applications. The authors describe the theoretical foundations and design methodology of such time-based ADCs from the basics to the latest developments. While most analog designers might notice some resemblance to PLL design, the book clearly highlights the differences to standard PLL circuit design and illustrates the design methodology with practical circuit design examples.Describes in detail the design methodology for CMOS time-encoding analog-to-digital converters that can be integrated along with digital logic in a nanometer System on Chip;Assists analog designers with the necessary change in design paradigm, highlighting differences between designing time-based ADCs and traditional analog circuits like switched-capacitor converters and PLLs;Uses a highly-visual, tutorial approach to the topic, including many practical examples of techniques introduced.

This book investigates the possible circuit solutions to overcome the temperature and supply voltage-sensitivity of fully-integrated time references for ultra-low-power communication in wireless sensor networks. The authors provide an elaborate theoretical introduction and literature study to enable full understanding of the design challenges and shortcomings of current oscillator implementations. Furthermore, a closer look to the short-term as well as the long-term frequency stability of integrated oscillators is taken. Next, a design strategy is developed and applied to 5 different oscillator topologies and 1 sensor interface. All 6 implementations are subject to an elaborate study of frequency stability, phase noise and power consumption. In the final chapter all blocks are compared to the state of the art.

Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design.

Analog integrated circuits are very important as interfaces between the digital parts of integrated electronic systems and the outside world. A large portion of the effort involved in designing these circuits is spent in the layout phase. Whereas the physical design of digital circuits is automated to a large extent, the layout of analog circuits is still a manual, time-consuming and error-prone task. This is mainly due to the continuous nature of analog signals, which causes analog circuit performance to be very sensitive to layout parasitics. The parasitic elements associated with interconnect wires cause loading and coupling effects that degrade the frequency behaviour and the noise performance of analog circuits. Device mismatch and thermal effects put a fundamental limit on the achievable accuracy of circuits. For successful automation of analog layout, advanced place and route tools that can handle these critical parasitics are required. In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In Analog Layout Generation for Performance and Manufacturability, the authors propose a performance driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. This approach makes a complete and sensible trade-off between the different layout alternatives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction. Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. In Analog Layout Generation for Performance and Manufacturability, the authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout. They then integrate this technique with their performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications. Analog Layout Generation for Performance and Manufacturability will be of interest to analog engineers, researchers and students.

This book brings together important contributions and state-of-the-art research results in the rapidly advancing area of symbolic analysis of analog circuits. It is also of interest to those working in analog CAD. The book is an excellent reference, providing insights into some of the most important issues in the symbolic analysis of analog circuits.

MATLAB simulation files

This book features recent research on computational intelligence techniques for the automated design of analog and high-frequency circuits. It will help readers handle state-of-the-art algorithms and even design their own methods.

This book covers modeling, simulation and analysis of analog circuit aging, nanometer CMOS physical effects resulting in unreliability, transistor aging compact models for circuit simulation, methods for efficient circuit reliability simulation and more.

This book describes computational intelligence-based tools for robust design of analog circuits. It starts with global variation-aware sizing and knowledge extraction and progressively extends to variation-aware topology design.

This book investigates the possible circuit solutions to overcome the temperature and supply voltage-sensitivity of fully-integrated time references for ultra-low-power communication in wireless sensor networks.

This text addresses the design methodologies and CAD tools available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches discussed increase analogue design productivity, demonstrated throughout using design times of the different design experiments undertaken.

This book can also serve as an excellent reference for researchers in the analog circuit design area and creators of CAD tools, as it provides a comprehensive overview and comparison of various approaches for analog circuit design automation and an extensive bibliography.

Various approaches for finding optimal values for the parameters of analog cells have made their entrance in commercial applications. This book examines the opportunities, conditions, problems, solutions and systematic methodologies for this new generation of analog CAD tools.

This book introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified. To validate the presented methodologies, the authors have selected and designed accordingly three different industrial-strength applications.

This text addresses the design methodologies and CAD tools available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches discussed increase analogue design productivity, demonstrated throughout using design times of the different design experiments undertaken.