Bücher von Peter Marwedel

This book focuses on source-to-source code transformations that remove addressing-related overhead present in most multimedia or signal processing application programs. This approach is complementary to existing compiler technology. What is particularly attractive about the transformation flow pre- sented here is that its behavior is nearly independent of the target processor platform and the underlying compiler. Hence, the different source code trans- formations developed here lead to impressive performance improvements on most existing processor architecture styles, ranging from RISCs like ARM7 or MIPS over Superscalars like Intel-Pentium, PowerPC, DEC-Alpha, Sun and HP, to VLIW DSPs like TI C6x and Philips TriMedia. The source code did not have to be modified between processors to obtain these results. Apart from the performance improvements, the estimated energy is also significantly reduced for a given application run. These results were not obtained for academic codes but for realistic and rep- resentative applications, all selected from the multimedia domain. That shows the industrial relevance and importance of this research. At the same time, the scientific novelty and quality of the contributions have lead to several excellent papers that have been published in internationally renowned conferences like e. g. DATE. This book is hence of interest for academic researchers, both because of the overall description of the methodology and related work context and for the detailed descriptions of the compilation techniques and algorithms.

Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation. In order to combine this growing system complexity with an increasingly short time-to-market, new system design technologies are emerging based on the paradigm of embedded programmable processors. This concept introduces modularity, flexibility and re-use in the electronic system design process. However, its success will critically depend on the availability of efficient and reliable CAD tools to design, programme and verify the functionality of embedded processors. Recently, new research efforts emerged on the edge between software compilation and hardware synthesis, to develop high-quality code generation tools for embedded processors. Code Generation for Embedded Systems provides a survey of these new developments. Although not limited to these targets, the main emphasis is on code generation for modern DSP processors. Important themes covered by the book include: the scope of general purpose versus application-specific processors, machine code quality for embedded applications, retargetability of the code generation process, machine description formalisms, and code generation methodologies. Code Generation for Embedded Systems is the essential introduction to this fast developing field of research for students, researchers, and practitioners alike.

It is well known that embedded systems have to be implemented efficiently. This requires that processors optimized for certain application domains are used in embedded systems. Such an optimization requires a careful exploration of the design space, including a detailed study of cost/performance tradeoffs. In order to avoid time-consuming assembly language programming during design space exploration, compilers are needed. In order to analyze the effect of various software or hardware configurations on the performance, retargetable compilers are needed that can generate code for numerous different potential hardware configurations. This book provides a comprehensive and up-to-date overview of the fast developing area of retargetable compilers for embedded systems. It describes a large set important tools as well as applications of retargetable compilers at different levels in the design flow. Retargetable Compiler Technology for Embedded Systems is mostly self-contained and requires only fundamental knowledge in software and compiler design. It is intended to be a key reference for researchers and designers working on software, compilers, and processor optimization for embedded systems.

Ein Alleinstellungsmerkmal dieses Open-Access-Lehrbuchs ist die umfassende Einführung in das Grundlagenwissen über eingebettete Systeme mit Anwendungen in cyber-physischen Systemen und dem Internet der Dinge. Es beginnt mit einer Einführung in das Gebiet und eine Übersicht über Spezifikationsmodelle und -sprachen für eingebettete und cyber-physikalische Systeme. Es gibt einen kurzen Überblick über die für solche Systeme verwendeten Hardware-Geräte und stellt die Grundlagen der Systemsoftware für eingebettete Systeme vor, einschließlich Echtzeit-Betriebssystemen. Der Autor erörtert auch Evaluierungs- und Validierungstechniken für eingebettete Systeme und gibt einen Überblick über Techniken zur Abbildung von Anwendungen auf Ausführungsplattformen, inklusive Multi-Core-Plattformen. Eingebettete Systeme müssen unter engen Randbedingungen arbeiten, daher enthält das Buch auch einen ausgewählten Satz von Optimierungstechniken, mit einem Schwerpunkt bei Software-Optimierungstechniken. Das Buch schließt mit einer kurzen Übersicht über das Testen. Die vierte Auflage wurde aktualisiert und überarbeitet, um neue Trends und Technologien zu berücksichtigen, wie z. B. die Bedeutung von cyber-physischen Systemen (CPS) und dem Internet der Dinge (IoT), die Entwicklung von Single-Core-Prozessoren hin zu Multi-Core-Prozessoren und die zunehmende Bedeutung von Energieeffizienz und thermischen Fragen.

A unique feature of this textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things.

Speed improvements in memory systems have not kept pace with the speed improvements of processors, leading to embedded systems whose performance is limited by the memory. In addition, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds.

This book proposes novel memory hierarchies and software optimization techniques for the optimal utilization of memory hierarchies. It presents a wide range of optimizations, progressively increasing in the complexity of analysis and of memory hierarchies.

This book presents the first comprehensive approach integrating WCET considerations into the code generation process. Based on the proposed reconciliation between a compiler and a timing analyzer, a wide range of novel optimization techniques is provided.