Bücher von Rainer Leupers

A subtle change that leads to disastrous consequences-hardware Trojans undoubtedly pose one of the greatest security threats to the modern age. How to protect hardware against these malicious modifications? One potential solution hides within logic locking; a prominent hardware obfuscation technique. In this book, we take a step-by-step approach to understanding logic locking, from its fundamental mechanics, over the implementation in software, down to an in-depth analysis of security properties in the age of machine learning. This book can be used as a reference for beginners and experts alike who wish to dive into the world of logic locking, thereby having a holistic view of the entire infrastructure required to design, evaluate, and deploy modern locking policies.

It is well known that embedded systems have to be implemented efficiently. This requires that processors optimized for certain application domains are used in embedded systems. Such an optimization requires a careful exploration of the design space, including a detailed study of cost/performance tradeoffs. In order to avoid time-consuming assembly language programming during design space exploration, compilers are needed. In order to analyze the effect of various software or hardware configurations on the performance, retargetable compilers are needed that can generate code for numerous different potential hardware configurations. This book provides a comprehensive and up-to-date overview of the fast developing area of retargetable compilers for embedded systems. It describes a large set important tools as well as applications of retargetable compilers at different levels in the design flow. Retargetable Compiler Technology for Embedded Systems is mostly self-contained and requires only fundamental knowledge in software and compiler design. It is intended to be a key reference for researchers and designers working on software, compilers, and processor optimization for embedded systems.

This book describes a flexible and largely automated methodology for adding the estimation of power consumption to high level simulations at the electronic system level (ESL). This method enables the inclusion of power consumption considerations from the very start of a design. This ability can help designers of electronic systems to create devices with low power consumption. The authors also demonstrate the implementation of the method, using the popular ESL language "SystemC". This implementation enables most existing SystemC ESL simulations for power estimation with very little manual work. Extensive case-studies of a Network on Chip communication architecture and a dual-core application processor "ARM Cortex-A9" showcase the applicability and accuracy of the method to different types of electronic devices. The evaluation compares various trade-offs regarding amount of manual work, types of ESL models, achieved estimation accuracy and impact on the simulation speed.Describes a flexible and largely automated ESL power estimation method;Shows implementation of power estimation methodology in SystemC;Uses two extensive case studies to demonstrate method introduced.

Offering techniques for programming Multi-Processor Systems-on-Chip (MPSoCs) capable of executing simultaneous multiple applications, this book includes methodologies to narrow the software productivity gap, and reviews challenges underlying current practices.

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice.

New software tools and a sophisticated methodology above RTL are required to answer the challenges of designing an optimized application specific processor (ASIP). This book offers an automated and fully integrated implementation flow and compares it to common implementation practice.

This comprehensive introduction to the design challenges of MPSoC platforms focuses on early space exploration and defines an iterative methodology to increase the abstraction level, enabling the evaluation of design decisions earlier in the design process.

Increasing complexity of modern embedded systems demands system designers to ramp up their design productivity without compromising performance goals.

This book presents a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation.

This book introduces a novel design methodology which can significantly reduce the ASIP development effort through high degrees of design automation. It includes several design case studies with real life embedded applications.

This book presents a novel approach for Architecture Description Language (ADL)-based instruction-set description that enables the automatic retargeting of the complete software toolkit from a single ADL processor model.

New software tools and a sophisticated methodology above RTL are required to answer the challenges of designing an optimized application specific processor (ASIP). This book offers an automated and fully integrated implementation flow and compares it to common implementation practice.

The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice.

Today more than 90% of all programmable processors are employed in embedded systems. The LISA processor design platform presented in this book addresses recent design challenges and results in highly satisfactory solutions, covering all major high-level phases of embedded processor design.