Bücher von Sanjay Churiwala

This book examines the impact of register transfer level (RTL) design choices that may result in issues of testability, data synchronization across clock domains, synthesizability, power consumption and routability, that appear later in the product lifecycle.

This guide to timing constraints in integrated circuit design shows how to maximize performance of IC designs by specifying timing requirements correctly. Coverage includes such design aspects as synthesis, static timing analysis and placement and routing.