Bücher von Tarun Chaudhary

Exponential growth in portable electronic system requires more and more functionality to be united in modern VLSI silicon chip. Junctionless transistors, therefore, help the chip makers continue to make smaller and smaller devices in order to improve the performance of a chip. JLDG VeSFET offers a novel concept which not only provide new 3-D integration friendly manufacturing but a unique design paradigm which provides effective electrostatic control over the channel and supreme reduction of short channel effects. A complete analysis of the aforementioned device is presented here with a view to meet the needs of next generation IC technology.

The book mainly focuses on the problem of high leakage which contributes to excessive standby power consumption. As it is known that the entire semiconductor industry is struggling with the heat of chips increasing exponentially as the number of transistors increases. The large leakage current may thus become a scaling showstopper, if alternative solutions are not provided to maintain it at an acceptable level. Although, to extend the scenario of transistor scaling and Moore¿s Law, a lot of research has been done in the recent past. Here in the book it is categorized as - research on alternative gate dielectrics like hafnium dioxide (HfO2), zirconium dioxide (ZrO2) and titanium dioxide (TiO2) and alternative device geometries like Double Gate MOSFET (DGMOSFET), tri-gate, gate all around) structures, silicon nanowire transistors (SNWT) etc. Effective gate control can be achieved by the multigate structures. High leakage current in deep-sub micrometer regimes is coming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced.