Bücher von Rolf Drechsler

In diesem Buch werden mehrere neue Ansätze vorgestellt, die den Weg für die nächste Generation integrierter Schaltungen ebnen, die auch in sicherheitskritischen Anwendungen erfolgreich und zuverlässig integriert werden können. Die Autoren beschreiben neue Maßnahmen zur Bewältigung der steigenden Herausforderungen im Bereich des Designs für Testbarkeit, Fehlersuche und Zuverlässigkeit, die für moderne Schaltungsentwürfe unbedingt erforderlich sind. Insbesondere werden in diesem Buch formale Techniken wie das Satisfiability (SAT)-Problem und das Bounded Model Checking (BMC) kombiniert, um die entstehenden Herausforderungen in Bezug auf die Zunahme des Testdatenvolumens, die Testanwendungszeit und die erforderliche Zuverlässigkeit zu bewältigen. Alle Methoden werden detailliert diskutiert und unter Berücksichtigung von industrie-relevanten Benchmark-Kandidaten ausführlich evaluiert. Alle Maßnahmen wurden in ein gemeinsames Framework integriert, das standardisierte Software/Hardware-Schnittstellen implementiert.

This book describes recent findings in the domain of Boolean logic and Boolean algebra, covering application domains in circuit and system design, but also basic research in mathematics and theoretical computer science. Content includes invited chapters and a selection of the best papers presented at the 14th annual International Workshop on Boolean Problems.

In VLSI CAD, difficult optimization problems have to be solved on a constant basis. Various optimization techniques have been proposed in the past. While some of these methods have been shown to work well in applications and have become somewhat established over the years, other techniques have been ignored. Recently, there has been a growing interest in optimization algorithms based on principles observed in nature, termed Evolutionary Algorithms (EAs). Evolutionary Algorithms in VLSI CAD presents the basic concepts of EAs, and considers the application of EAs in VLSI CAD. It is the first book to show how EAs could be used to improve IC design tools and processes. Several successful applications from different areas of circuit design, like logic synthesis, mapping and testing, are described in detail. Evolutionary Algorithms in VLSI CAD consists of two parts. The first part discusses basic principles of EAs and provides some easy-to-understand examples. Furthermore, a theoretical model for multi-objective optimization is presented. In the second part a software implementation of EAs is supplied together with detailed descriptions of several EA applications. These applications cover a wide range of VLSI CAD, and different methods for using EAs are described. Evolutionary Algorithms in VLSI CAD is intended for CAD developers and researchers as well as those working in evolutionary algorithms and techniques supporting modern design tools and processes.

Formal verification has become one of the most important steps in circuit design. Since circuits can contain several million transistors, verification of such large designs becomes more and more difficult. Pure simulation cannot guarantee the correct behavior and exhaustive simulation is often impossible. However, many designs, like ALUs, have very regular structures that can be easily described at a higher level of abstraction. For example, describing (and verifying) an integer multiplier at the bit-level is very difficult, while the verification becomes easy when the outputs are grouped to build a bit-string. Recently, several approaches for formal circuit verification have been proposed that make use of these regularities. These approaches are based on Word-Level Decision Diagrams (WLDDs) which are graph-based representations of functions (similar to BDDs) that allow for the representation of functions with a Boolean range and an integer domain. Formal Verification of Circuits is devoted to the discussion of recent developments in the field of decision diagram-based formal verification. Firstly, different types of decision diagrams (including WLDDs) are introduced and theoretical properties are discussed that give further insight into the data structure. Secondly, implementation and minimization concepts are presented. Applications to arithmetic circuit verification and verification of designs specified by hardware description languages are described to show how WLDDs work in practice. Formal Verification of Circuits is intended for CAD developers and researchers as well as designers using modern verification tools. It will help people working with formal verification (in industry or academia) to keep informed about recent developments in this area.

This book introduces a new level of abstraction that closes the gap between the textual specification of embedded systems and the executable model at the Electronic System Level (ESL). Readers will be enabled to operate at this new, Formal Specification Level (FSL), using models which not only allow significant verification tasks in this early stage of the design flow, but also can be extracted semi-automatically from the textual specification in an interactive manner.  The authors explain how to use these verification tasks to check conceptual properties, e.g. whether requirements are in conflict, as well as dynamic behavior, in terms of execution traces.

This book describes a set of SystemC-based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL).

This book presents exact, that is minimal, solutions to individual steps in the design process for Digital Microfluidic Biochips (DMFBs), as well as a one-pass approach that combines all these steps in a single process. All of the approaches discussed are based on a formal model that can easily be extended to cope with further design problems. In addition to the exact methods, heuristic approaches are provided and the complexity classes of various design problems are determined.Presents exact methods to tackle a variety of design problems for Digital Microfluidic Biochips (DMFBs);Describes an holistic, one-pass approach solving different design steps all at once;Based on a formal model of DMFBs that is easily adaptable to deal with further design tasks.

This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine.

The authors enable readers to follow two "directions" for refinement: Vertical refinement, for adding detail and precision to single description for a given model and Horizontal refinement, which considers several views on one level of abstraction, refining the system specification by dedicated descriptions for structure or behavior.

This book introduces a new level of abstraction that closes the gap between the textual specification of embedded systems and the executable model at the Electronic System Level (ESL).

This bookpresents a new optimization flow for quantum circuits realization. Then, new mapping approaches to decompose reversible circuits to quantumcircuits using different quantum libraries are described. Finally, optimizationtechniques to reduce the quantum cost or the delay are applied to the resultingquantum circuits.

With increasing number of applications, also in non CAD areas, classical methods to handle BDDs are being improved and new questions and problems evolve and have to be solved.

VLSI CADhas greatly bene?ted from the use of reduced ordered Binary Decision Diagrams (BDDs) and the clausal representation as a problem of Boolean Satis?ability (SAT), e.g. Latest results in BDD optimization are given, c- ering di?erent aspects of paths in BDDs and the use of e?cient lower bounds during optimization.

This text offers a quality-driven design and verification flow for digital systems. Dedicated verification techniques are integrated which target the different levels of abstraction, and each technique has a means to measure the achieved verification quality.

This book presents contributions to a design flow for reversible logic, including advanced methods for synthesis, optimization, verification, and debugging. It proposes several techniques for synthesis of very large functions in reversible logic.

Providing an introduction to ATPG, this book reviews the basic concept and classical ATPG algorithms. It is the first book to give a detailed overview on SAT-based ATPG. It describes the state-of-the-art in the field and shows directions for future work.

Debugging is the bottleneck to chip design productivity. This state-of-the-art book reviews modeling and verification of ESL designs. It is believed to be the first book that considers debugging for ESL designs. There is particular focus on SystemC.

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). It presents a fast and highly fault efficient SAT-based ATPG framework.

The size of technically producible integrated circuits increases continuously, but the ability to design and verify these circuits does not keep up. Using a visionary approach, this book analyzes the current design methodology and verification methodology, a number of deficiencies are identified and solutions suggested.

The design process of digital circuits is often carried out in individual steps, like logic synthesis, mapping, and routing.