Bücher von Saranya Karunamurthi

Multiplikatoren mit großen Bitlängen haben einen großen Einfluss auf die Leistung digitaler Schaltungen in vielen Anwendungen wie Kryptographie, digitale Signalverarbeitung und Bildverarbeitung. Die Leistung vieler Berechnungsprobleme wird häufig von der Geschwindigkeit bestimmt, mit der eine Multiplikationsoperation ausgeführt werden kann. Dieses Buch gibt einen kurzen Überblick über verschiedene Multiplikatoren wie Baugh-Woley-, Pezaris-, Array-, Booth-, Vedic-Multiplikatoren und Kompressor-basierte Multiplikatoren. Das Hauptziel besteht darin, verschiedene Arten von Multiplizierern in Bezug auf Leistungsaufnahme, Fläche und Verzögerung zu vergleichen. Diese vorzeichenbehafteten Multiplikationskonzepte werden in Verilog HDL implementiert und in Cadence RTL Compiler mit 180nm Technologie umgesetzt.

I moltiplicatori con grandi lunghezze di bit hanno un grande impatto sulle prestazioni dei circuiti digitali in molte applicazioni come la crittografia, l'elaborazione digitale dei segnali e l'elaborazione delle immagini. Le prestazioni di molti problemi di calcolo sono spesso dominate dalla velocità di esecuzione di un'operazione di moltiplicazione. Questo libro offre una breve panoramica di vari moltiplicatori come Baugh Wooley, Pezaris, Array, Booth, moltiplicatori vedici e moltiplicatori basati su compressori. L'obiettivo principale è quello di confrontare i vari tipi di moltiplicatori in termini di consumo energetico, area e ritardo. Questi concetti di moltiplicazione firmata sono implementati in Verilog HDL e realizzati in Cadence RTL Compiler con tecnologia a 180 nm.

Os multiplicadores com grande comprimento de bits têm um grande impacto no desempenho dos circuitos digitais em muitas aplicações como a criptografia, o processamento de sinais digitais e o processamento de imagens. As performances de muitos problemas computacionais são frequentemente dominadas pela velocidade a que uma operação de multiplicação pode ser executada. Este livro dá uma breve visão geral de vários multiplicadores tais como Baugh Wooley, Pezaris, Array, Booth, multiplicadores Vedic e multiplicadores baseados em Compressores. O principal objectivo é comparar vários tipos de multiplicadores em termos de consumo de energia, área e atraso. Estes conceitos de multiplicação assinados são implementados em Verilog HDL e implementados em Cadence RTL Compiler com tecnologia de 180nm.

Les multiplicateurs à grande longueur de bit ont un impact majeur sur les performances des circuits numériques dans de nombreuses applications comme la cryptographie, le traitement des signaux numériques et le traitement des images. Les performances de nombreux problèmes de calcul sont souvent dominées par la vitesse à laquelle une opération de multiplication peut être exécutée. Ce livre donne un bref aperçu de divers multiplicateurs tels que Baugh Wooley, Pezaris, Array, Booth, multiplicateurs védiques et multiplicateurs basés sur des compresseurs. L'objectif principal est de comparer les différents types de multiplicateurs en termes de consommation d'énergie, de surface et de délai. Ces concepts de multiplication signés sont implémentés en Verilog HDL et mis en ¿uvre dans le Cadence RTL Compiler avec la technologie 180nm.

Los multiplicadores con grandes longitudes de bits tienen un gran impacto en el rendimiento de los circuitos digitales en muchas aplicaciones como la criptografía, el procesamiento digital de señales y el tratamiento de imágenes. El rendimiento de muchos problemas computacionales suele estar dominado por la velocidad a la que puede ejecutarse una operación de multiplicación. Este libro ofrece una breve descripción de varios multiplicadores como Baugh Wooley, Pezaris, Array, Booth, multiplicadores védicos y multiplicadores basados en compresores. El objetivo principal es comparar varios tipos de multiplicadores en términos de consumo de energía, área y retardo. Estos conceptos de multiplicación con signo se implementan en Verilog HDL y se implementan en Cadence RTL Compiler con tecnología de 180nm.

Multipliers with large bit lengths have a major impact on the performance of digital circuits in many applications like cryptography, digital signal processing and image processing. The performances of many computational problems are often dominated by the speed at which a multiplication operation can be executed. This book gives a brief overview of various multipliers such as Baugh Wooley, Pezaris, Array, Booth, Vedic multipliers and Compressor based multipliers. The main objective is to compare various types of multiplier in terms of power consumption, area and delay. These signed multiplication concepts are implemented in Verilog HDL and implemented in Cadence RTL Compiler with 180nm technology.

Project Report from the year 2018 in the subject Engineering - General, Basics, grade: UG, , language: English, abstract: This project helps in simplifying the process of learning of braille instructions. The integration of physical activity and hearing can facilitate easy learning of Braille Script. In this project we develop a kit which helps the blind and visually impaired people to learn braille even in the absence of teachers.Braille literacy is crucial for blind individuals, as it enables life-long learning and is key to employment and independency. One way to promote Braille literacy is to make existing Braille reading devices more accessible, affordable, and user friendly. Commercially available Braille reading devices in this regard need various improvements. Most of these devices cost thousands of dollars, mainly because they rely on multiple piezoelectric actuators in order to create the Braille letters. Other issues include high voltage actuation and reduced portability. In order to solve these issues and improve existing Braille displays, various actuation methods have been widely investigated.285 million people are estimated to be visually impaired worldwide, 39 million are blind and 246 have low vision. India has the largest population of blind people in the world. That's over 12 million people. Even the central and state government provide job opportunities for blind and visually impaired people. But only few vacancies are filled due to lack of education. Lack of education for blind people is due to the lack of qualified teachers to teach them Braille. Learning the Braille script is not an easy task for Visually Impaired students. Visually Impaired students have to memorize various patterns of keys of Braille matrix assigned for different letters/words/symbols in Braille script to read and write effectively.

A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional.