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OPENGL GPU Architecture and Implementation of Line Rasterization

Über OPENGL GPU Architecture and Implementation of Line Rasterization

The GPU has become an essential block for the embedded system devices. The GPU¿s main purpose is to accelerate the rendering of images, animations and videos. This process is essential for many devices such as smart phones, tablets, and gaming devices. This book introduces CUGPU, the Cairo University GPU, architecture based on Common-Lite (CL) pröle of the Open Graphics Library for Embedded System 1.1 (OpenGL ES 1.1). CUGPU provides high-performance support of the ¿xed-function 3D graphics pipeline. Moreover, CUGPU can be integrated with the Cairo University SPARC (CUSPARC) processor into a complete embedded system. Two designs of the line rasterization algorithm were implemented using VHDL code and synthesized at the TSMC 65 nm low power technology node. The first design scores a typical clock frequency of 270 MHz and an area of 0.088 mm2. The second design scores a typical clock frequency of 200 MHz and an area of 0.052 mm2.

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  • Sprache:
  • Englisch
  • ISBN:
  • 9783330853911
  • Einband:
  • Taschenbuch
  • Seitenzahl:
  • 176
  • Veröffentlicht:
  • 27. März 2017
  • Abmessungen:
  • 150x12x220 mm.
  • Gewicht:
  • 280 g.
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Beschreibung von OPENGL GPU Architecture and Implementation of Line Rasterization

The GPU has become an essential block for the embedded system devices. The GPU¿s main purpose is to accelerate the rendering of images, animations and videos. This process is essential for many devices such as smart phones, tablets, and gaming devices. This book introduces CUGPU, the Cairo University GPU, architecture based on Common-Lite (CL) pröle of the Open Graphics Library for Embedded System 1.1 (OpenGL ES 1.1). CUGPU provides high-performance support of the ¿xed-function 3D graphics pipeline. Moreover, CUGPU can be integrated with the Cairo University SPARC (CUSPARC) processor into a complete embedded system. Two designs of the line rasterization algorithm were implemented using VHDL code and synthesized at the TSMC 65 nm low power technology node. The first design scores a typical clock frequency of 270 MHz and an area of 0.088 mm2. The second design scores a typical clock frequency of 200 MHz and an area of 0.052 mm2.

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