Bücher der Reihe Frontiers in Electronic Testing

The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield.

Emerging Nanotechnologies: Test, Defect Tolerance and Reliability covers various technologies that have been developing over the last decades such as chemically assembled electronic nanotechnology, Quantum-dot Cellular Automata (QCA), and nanowires and carbon nanotubes.

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

Emerging Nanotechnologies: Test, Defect Tolerance and Reliability covers various technologies that have been developing over the last decades such as chemically assembled electronic nanotechnology, Quantum-dot Cellular Automata (QCA), and nanowires and carbon nanotubes.

The second part contains all the mathematical details that are necessary to prove the validity of the analysis techniques, the existence of solutions to the problems that those techniques engender, and the correctness of several properties that were assumed in the first part.

This is a comprehensive guide to fault injection techniques used to evaluate the dependability of a digital system. The description and the critical analysis of different fault injection techniques and tools are authored by key scientists in the field of system dependability and fault tolerance.

Then, once the Standard was accepted I became the central point of contact for people who just picked up the Standard, who didn't have the benefit of the Working Group discussions, who only had available that one final sentence in the Standard and who didn't benefit from the perspective of where those words came from.

Model based testing is the most powerful technique for testing hardware and software systems. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed.

A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging.

Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing.

In many applications, the classic branch-and-bound search methods perform duplications of computations, or rely on the search decision trees which keep track of the branch-and-bound search processes.

In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

This book presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short.

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. This book focuses on practical design considerations inherent to the application of IEEE Std. The authors provide background information about some of the choices and decisions made throughout the design of IEEE Std.

Design for AT-Speed Test, Diagnosis and Measurement is the first book to offer practical and proven design-for-testability (DFT) solutions to chip and system design engineers, test engineers and product managers at the silicon level as well as at the board and systems levels.

In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing.

Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing.

The modern electronic testing has a forty year history. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook.

This book presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short.

In many applications, the classic branch-and-bound search methods perform duplications of computations, or rely on the search decision trees which keep track of the branch-and-bound search processes.

Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield.

This increase in the use of IDDQ testing should be of interest to three groups of individuals associated with the IC business: Product Managers and Test Engineers, CAD Tool Vendors and Circuit Designers.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging.

Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.

This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.